M16C65 Datasheet, PDF (562/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.3 Special Mode 1 (I²C mode)
I²C mode supports the simplified I²C interface. Table 23.14 lists the specifications of I²C mode. Table
23.16 and Table 23.17 list the registers used in I²C mode and the register settings. Table 23.18 lists the
I²C Mode Specifications. Figure 23.18 shows I²C Mode Block Diagram. Figure 23.19 shows Transfer to
UiRB Register and Interrupt Timing.
As shown in Table 23.18, the MCU is placed in I²C mode by setting bits SMD2 to SMD0 to 010b and the
IICM bit to 1. Because SDAi transmit output has a delay circuit attached, SDAi output changes its state
after SCLi goes low and remains stably low.
Table 23.14 I²C Mode Specifications
Item
Data format
Transmit/receive clock
Specification
Character bit length: 8 bits
• Master mode
CKDIR bit in the UiMR register = 0 (internal clock):
-₂---₍---_n---^f-₊-^j----₁----₎- _{fj = f1SIO, f2SIO, f8SIO, f32SIO}
n = setting value of the UiBRG register 00h to FFh
• Slave mode
CKDIR bit = 1 (external clock): Input from the SCLi pin
Transmission start
conditions
To start transmission, satisfy the following requirements. ⁽¹⁾
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
Reception start conditions _{To start reception, satisfy the following requirements.} ⁽¹⁾
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Interrupt request
Transmission interrupt
generation timing
• Acknowledge undetected or transmit
Reception interrupt
• Acknowledge undetected or receive
Start/stop condition detection interrupt
• Start or stop condition detected
Error detection
Overrun error ⁽²⁾
This error occurs if the serial interface starts receiving the next unit of data
before reading the UiRB register and receives the 8th bit of the unit of next
data.
Selectable functions
• Arbitration lost
Timing that the ABT bit in the UiRB register is updated can be selected.
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles can
be selected.
• Clock phase setting
With or without clock delay can be selected.
i = 0 to 2, 5 to 7
Notes:
1. When an external clock is selected, the conditions must be met while the external clock is in the
high state.
2. If an overrun error occurs, the received data of the UiRB register will be undefined.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 527 of 791