M16C65 Datasheet, PDF (332/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17.2.11 One-Shot Start Flag (ONSF)
17. Timer A
One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Address
0322h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
TA0OS
Timer A0 one-shot start flag
The timer starts counting by setting this bit
to 1. Read as 0
RW
TA1OS Timer A1 one-shot start flag
RW
TA2OS Timer A2 one-shot start flag
RW
TA3OS Timer A3 one-shot start flag
RW
TA4OS Timer A4 one-shot start flag
RW
TAZIE Z-phase input enable bit
0 : Z-phase input disabled
1 : Z-phase input enabled
RW
TA0TGL
TA0TGH
b7
Timer A0 event/trigger select
bit
0
0
1
1
b6
0 : Input on TA0IN pin selected
1 : Timer B2 selected
0 : Timer A4 selected
1 : Timer A1 selected
RW
RW
i = 0 to 4
TAiOS (Timer Ai One-Shot Start Flag) (b4-b0) (i = 0 to 4)
This bit is enabled in one-shot timer mode. When the MR2 bit in the TAi register is 0 (TAiOS bit
enabled), the timer Ai count starts by setting the TAiOS bit to 1 after setting the TAiS bit in the TABSR
register to 1 (start counting).
TAZIE (Z-Phase Input Enable Bit) (b5)
This bit is used in event counter mode (two-phase pulse signal processing) of timer A3. Refer to
17.3.4.3 “Counter Initialization by Two-Phase Pulse Signal Processing” for details.
TA0TGH-TA0TGL (Timer A0 Event/Trigger Select Bit) (b7-b6)
This bit is used to select an event or a trigger of the following modes:
• An event in event counter mode (not using two-phase pulse signal processing)
• A trigger in one-shot timer mode or PWM mode
The above applies when the MR2 bit in the TA0MR register is 1 (trigger selected by bits TA0TGH to
TA0TGL).
The active edge of input signals can be selected by the MR1 bit in the TA0MR register when bits
TA0TGH to TA0TGL are 00b.
When bits TA0TGH to TA0TGL are set to 01b, 10b, or 11b, an event or a trigger occurs when an
interrupt request of the selected timer is generated. (An event or a trigger occurs while an interrupt is
disabled because bits TA0TGH to TA0TGL are not influenced by I flag, IPL, or the interrupt control
registers.)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 297 of 791