M16C65 Datasheet, PDF (130/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
7. Voltage Detector
7.4.4.2 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 7.8 lists Steps to Set Voltage Monitor 2 Interrupt/Reset Related Bits.
Table 7.8 Steps to Set Voltage Monitor 2 Interrupt/Reset Related Bits
When Using the Digital Filter
When Not Using the Digital Filter
Step
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
Voltage Monitor 2
Interrupt
Voltage Monitor 2
Reset
1
Set the CM14 bit in the CM1 register to 0 (125 -
kHz on-chip oscillator on)
2
Wait for digital filter sampling clock x 3 cycles. - (no wait time)
3
Set the VW12E bit in the VWCE register to 1 (voltage detection circuit enabled).
4
Set the VC27 bit in the VCR2 register to 1 (voltage detection 2 circuit enabled).
5
Wait for td(E (E-A).
6
Use bits VW2F0 to VW2F1 in the VW2C
Use the VW2C7 bit in the VW2C register to
register to select the digital filter sampling
select the timing of the interrupt and reset
clock.
request. ⁽¹⁾
7 ^{(2) Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1}
(digital filter enabled).
(digital filter disabled).
8 ^{(2) Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in}
the VW2C register to 0 the VW2C register to 1 the VW2C register to 0 the VW2C register to 1
(voltage monitor 2 (voltage monitor 2 (voltage monitor 2 (voltage monitor 2
interrupt mode).
reset mode).
interrupt mode).
reset mode).
9
Set the VW2C2 bit in the VW2C register to 0 (Vdet2 passage not detected).
10
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled).
Notes:
1.
2.
Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
When the VW2C0 bit is 0, procedures 6, 7, and 8 can be executed simultaneously (with one
instruction).
When using voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1
bit in the VW2C register to 1 (digital filter disabled).
When voltage monitor 2 reset is generated, the LVD2R bit in the RSTFR register is automatically set
to 1 (voltage monitor 2 reset detected). Refer to 6.4.6 “Voltage Monitor 2 Reset” for status after reset.
Figure 7.8 shows Voltage Monitor 2 Interrupt/Reset Operation Example.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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