M16C65 Datasheet, PDF (300/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
16. DMAC
16. DMAC
16.1 Introduction
The direct memory access controller (DMAC) allows data to be transferred without CPU intervention.
Four DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-
bit) unit of data from the source address to the destination address. The DMAC uses the same data bus
used by the CPU. Because the DMAC has higher priority for bus control than the CPU, and because it
makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a
very short time after a DMA request is generated. Figure 16.1 shows the DMAC Block Diagram. Table
16.1 lists DMAC Specifications, and Figure 16.1 shows DMAC Block Diagram.
Table 16.1 DMAC Specifications
Item
Specification
Number of channels
4 (cycle steal method)
Transfer memory spaces
• From a given address in the 1-Mbyte space to a fixed address
• From a fixed address to a given address in the 1-Mbyte space
• From a fixed address to a fixed address
Maximum number of
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
bytes transferred
DMA request factors ⁽¹⁾
43 factors
Falling edge of INT0 to INT7 (8)
Both edges of INT0 to INT7 (8)
Timer A0 to timer A4 interrupt requests (5)
Timer B0 to timer B5 interrupt requests (6)
UART0 to 2, UART5 to 7 transmission interrupt requests (6)
UART0 to 2, UART5 to 7 reception/ACK interrupt requests (6)
SI/O3, SI/O4 interrupt requests (2)
A/D conversion interrupt requests (1)
Software triggers (1)
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 takes precedence)
Transfers
8 bits or 16 bits
Transfer address direction Forward or fixed (The source and destination addresses cannot both be in the
forward direction.)
Transfer Single transfer Transfer is completed when the DMAi transfer counter underflows.
mode
Repeat
When the DMAi transfer counter underflows, it is reloaded with the value of the
transfer
DMAi transfer counter reload register and DMA transfer continues.
DMA interrupt request When the DMAi transfer counter underflows
generation timing
DMA transfer start
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register is 1 (enabled).
DMA
transfer
stop
Single transfer • When the DMAE bit is set to 0 (disabled)
• After the DMAi transfer counter underflows
Repeat
When the DMAE bit is set to 0 (disabled)
transfer
Reload timing for forward When a data transfer is started after setting the DMAE bit to 1 (enabled), the
address pointer and DMAi forward address pointer is reloaded with the value of the SARi or DARi pointer
transfer counter
whichever is specified to be in the forward direction and the DMAi transfer
counter is reloaded with the value of the DMAi transfer counter reload register.
DMA transfer cycles
Minimum 3 cycles between SFR and internal RAM
i = 0 to 3
Note:
1. The selectable sources of DMA requests differ for each channel.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 265 of 791