M16C65 Datasheet, PDF (281/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.7.9 Multiple Interrupts
The following shows the internal bit states when control has branched to an interrupt routine.
• I flag
= 0 (interrupt disabled)
• IR bit
= 0 (interrupt not requested)
• Interrupt priority level= IPL
By setting the I flag to 1 (interrupt enabled) in the interrupt routine, an interrupt request with higher
priority than the IPL can be acknowledged.
The interrupt requests not acknowledged because of their low interrupt priority level are kept pending.
When the IPL is restored by an REIT instruction and interrupt priority is resolved against it, the pending
interrupt request is acknowledged if the following condition is met:
Interrupt priority level of pending interrupt request > Restored IP
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 246 of 791