M16C65 Datasheet, PDF (127/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
7. Voltage Detector
7.4.3.2 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 7.7 lists Steps to Set Voltage Monitor 1 Interrupt/Reset Related Bits.
Table 7.7 Steps to Set Voltage Monitor 1 Interrupt/Reset Related Bits
When Using the Digital Filter
When Not Using the Digital Filter
Step
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
Voltage Monitor 1
Interrupt
Voltage Monitor 1
Reset
1
Set the CM14 bit in the CM1 register to 0 (125 -
kHz on-chip oscillator on)
2
Wait for digital filter sampling clock x 3 cycles. - (no wait time)
3
Set the VW12E bit in the VWCE register to 1 (voltage detection 1 and 2 circuits enabled).
4
Set bits VD1LS3 to VD1LS0 in the VD1LS register to select Vdet1.
5
Set the VC26 bit in the VCR2 register to 1 (voltage detection 1 circuit enabled).
6
Wait for td(E (E-A).
Use bits VW1F0 to VW1F1 in the VW1C
Use the VW1C7 bit in the VW1C register to
7
register to select the digital filter sampling
select the timing of the interrupt and reset
clock.
request. ⁽¹⁾
8 ⁽²⁾
Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1
(digital filter enabled).
(digital filter disabled).
Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in
9 ⁽²⁾
the VW1C register to 0 the VW1C register to 1 the VW1C register to 0 the VW1C register to 1
(voltage monitor 1 (voltage monitor 1 (voltage monitor 1 (voltage monitor 1
interrupt mode).
reset mode).
interrupt mode).
reset mode).
10
Set the VW1C2 bit in the VW1C register to 0 (Vdet1 passage not detected).
11
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled).
Notes:
1.
2.
Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
When the VW1C0 bit is 0, procedures 7, 8, and 9 can be executed simultaneously (with one
instruction).
When using voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1
bit in the VW1C register to 1 (digital filter disabled).
When voltage monitor 1 reset is generated, the LVD1R bit in the RSTFR register is automatically set
to 1 (voltage monitor 1 reset detected). Refer to 6.4.5 “Voltage Monitor 1 Reset” for status after reset.
Figure 7.6 shows Voltage Monitor 1 Interrupt/Reset Operation Example.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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