M16C65 Datasheet, PDF (524/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
f1
fOCO-F
OCOSEL0
1/2 ^f2SIO
f1SIO
1/8
PCLK1
0
1
1/4
f1SIO or f2SIO
f8SIO
f32SIO
RXD1
RXD polarity
switching circuit
Clock source selection
f1SIO or
f2SIO
f8SIO
f32SIO
CLK1 to CLK0 _CKDIR
00
Internal
01
0
10
1
External
U1BRG
register
1/(n+1)
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock sync type
001
Reception
control circuit
UART transmission
010, 100, 101, 110
1/16
Clock sync type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
0
Clock synchronous type
(when external clock is selected)
1
Receive
clock
Transmit
clock
CLK1
CTS1/RTS1/
CTS0/CLKS1
CKPOL
CLK
polarity
reversing
circuit
Clock output
pin select
0 ^CLKMD0
Clock synchronous type
(when internal clock is selected)
1
1 ^{CTS/RTS selected} _{CTS/RTS disabled}
CRS ₁
0
CLKMD1
0
0 ^{CTS/RTS disabled}
CKDIR
RTS1
0 CTS1
n: Value set to the U1BRG register
1
VSS
CRD
1
RCSP
to CTS0 in UART0
PCLK1
: Bit in the PCLKR register
SMD2 to SMD0, CKDIR
: Bits in the U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the U1C0 register
CLKMD0, CLKMD1, RCSP
: Bits in the UCON register
OCOSEL0
: Bit in the UCLKSEL0 register
Transmit/
receive
unit
Figure 23.2 UART1 Block Diagram
TXD _TXD1
polarity
switching
circuit
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 489 of 791