M16C65 Datasheet, PDF (650/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.4 Interrupts
I²C interface generates an interrupt request. Figure 25.21 shows I²C Interface Interrupts, and Table 25.16
lists I²C-bus Interrupts.
I²C-bus Interrupt
ACKCLK bit in the S20 register
Falling edge of the last bit clock of
transmit/receive data detected
Falling edge of the ACK
clock detected
WIT bit in the S3D0 register
Falling edge of the last bit clock of
received data detected
TRX bit in the S10 register
MST bit in the S10 register
ASL bit in the S1D0 register
AAS bit in the S10 register
ADR0 bit in the S10 register
Slave address reception
completed
Slave address transmission
completed
SIM bit in the S3D0 register
Stop condition detected
TOE bit in the S4D0 register
Timeout detected
(Data transmit/receive
completed)
(Data received)
(Slave address match
detected)
(General call detected)
(Slave address reception
completed by address
match detection disabled)
SCPIN bit in the S4D0 register
(Stop condition detected)
TOF bit in the S4D0 register
(Timeout detected)
PIN
I²C-bus interrupt
request (to the IR bit in
the IICIC register)
SCL/SDA Interrupt
SCLMM
SDAMM
S2D0 register
SIS=1
SIS=0
Figure 25.21 I²C Interface Interrupts
SIP bit in the
S2D0 register
Edge selector
SCL/SDA interrupt
request (to IR bit in the
SCLDAIC register)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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