M16C65 Datasheet, PDF (645/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.10 Data Transmit/Receive Examples
The data transmit/receive examples are described in this section. The conditions for the examples are
follows.
• Slave address: 7 bits
• Data: 8 bits
• ACK clock
• Standard clock mode, bit rate: 100 kbps (fIIC: 20 MHz, fVIIC: 4 MHz)
20 MHz (fIIC) divided-by-5 = 4 MHz (fVIIC),
4 MHz (fVIIC) divided-by-8 and further divided-by-5 =100 kbps (bit rate)
• In receive mode, ACK response is sent for other than the last data. NACK is returned after the last
data is received.
• When receiving data, I²C-bus interrupt at 8th clock (just before ACK clock): disabled
• Stop condition interrupt: enabled
• Timeout interrupt: disabled
• Set an own slave address to the S0D0 register (registers S0D1 or S0D2 should not be used)
If an I²C-bus interrupt at 8th clock (just before ACK clock) is enabled in data receive, a receiver
generates ACK or NACK after each byte of data has been received.
25.3.10.1 Initial Setting
Follow the initial setting procedures below for 25.3.10.2 to 25.3.10.5.
(1) Write an own slave address to bits SAD6 to SAD0 in the S0D0 register.
(2) Write 85h to the S20 register. (CCR value: 5, standard mode selected, ACK clock presents)
(3) Write 18h to the S4D0 register. (fVIIC: fIIC divided-by-5, timeout interrupt disabled)
(4) Write 01h to the S3D0 register. (stop condition detect interrupt enabled and I²C-bus interrupt at
8th clock is disabled when receiving data)
(5) Write 0Fh to the S10 register. (slave-receiver mode)
(6) Write 98h to the S2D0 register (SSC value: 18h, start/stop condition generation timing: long
mode)
(7) Write 08h to the S1D0 register (bit counter: 8, I²C interface enabled, addressing format, input
level: I²C-bus input)
If the MCU uses a single-master system and it is a master, start the initial setting procedures from (2).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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