M16C65 Datasheet, PDF (619/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
When setting the WIT bit to 1 in receive mode, and ACK clock is present:
(I²C-bus interrupt is enabled at 8th clock)
SCLMM
7
SDAMM
7th bit
8
8th bit
9
ACK
clock
1st bit
ACKBIT bit in the S20 register
PIN bit in the S10 register
Write by a program
Internal WAIT flag
IR bit in the IICIC register
Write signal to the S00 register
(1)
(2)
Set to 0 by an interrupt acceptance or by a program
When setting the WIT bit to 0 in receive mode, and ACK clock is present:
(I²C-bus interrupt is disabled at 8th clock)
SCLMM
7
SDAMM
7th bit
8
8th bit
9
ACK
clock
ACK bit
1
1st bit
ACKBIT bit in the S20 register
0
PIN bit in the S10 register
Internal WAIT flag
0
IR bit in the IICIC register
Write signal to the S00 register
(2)
Set to 0 by an interrupt acceptance or by a program
Figure 25.4 Interrupt Request Generation Timing in Receive Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 584 of 791