M16C65 Datasheet, PDF (358/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
65535-n
n
65535
Count start
65535
65535
Reload count start
when a value
except 0000h is written.
0000h
TAiS bit
in TABSR register
TAiIN input
TAiOUT output
POFSi = 0
POFSi = 1
IR bit
in TAiIC register
Count stop
n
65535-n
Write 0000h in the TAi
register during this period.
Reload 0000h and
stop counting.
Set to 0
by a program
Cannot be a re-trigger
after count start
Count stop
Low-level output
at count stop
Low-level output
at count stop
High-level output
at count stop
Interrupt request generated
n
- When TAiOUT changes state
fj
65535
from high to low while POFSi is 0.
fj
- When TAiOUT changes state
from low to high while POFSi is 1.
Interrupt request generated
(The IR bit does not change
- when TAiOUT changes state from high to low while POFSi is 0.
when output has no change.)
- when TAiOUTchanges state fromlowto high while POFSi is 1. No intrrupt request
i = 0 to 4
Set to 0 by an interrupt request acknowledgement or by a program.
The above timing diagram applies when the register bits are set as follows:
- The MR0 bit in the TAiMR register = 1 (pulse output)
- The MR3 bit in the TAiMR register = 0 (16-bit PWM mode)
- The MR1 bit in the TAiMR register = 1
- The MR2 bit in the TAiMR register = 1
(The rising edge of the TAiIN pin input is the trigger.)
- Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b
15
0
TAi register
n
Operates as 16-bit pulse width modulator
fj: Count source frequency
Figure 17.11 Operation Example in 16-Bit Pulse Width Modulation Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 323 of 791