M16C65 Datasheet, PDF (647/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.10.3 Master Reception
The master reception is described in this section. The initial settings described in 25.3.10.1 “Initial
Setting” are assumed to be completed. Figure 25.18 shows the operation example of master
reception. The following programs (A) to (D) are executed at the (A) to (D) in Figure 25.18,
respectively.
S: Start condition
P: Stop condition
m
S
Slave address
(7 bits)
A: ACK
A: NACK
R: Read
W: Write
s
m
RA
Data
(8 bits)
A
m: Master outputs to SDA
s: Slave outputs to SDA
s
m
Data
(8 bits)
AP
SCLMM
SDAMM
IR bit in the IICIC
register
Set to 0 by interrupt request acceptance or by program
(B) Data reception 1
(A) Slave address transmission
Figure 25.18 Example of Master Reception
(C) Data reception 2
(D) End of master reception
Stop condition
(A) Slave address transmission
(1) The BB bit in the S10 register must be 0 (bus free).
(2) Write E0h to the S10 register. (Start condition standby)
(3) Write a slave address to the seven most significant bits (MSB) and a 0 to the least significant bit
(LSB). (Start condition generated, then slave address transmitted)
(B) Data reception 1 (after slave address transmission)
(In I²C-bus interrupt routine)
(1) Write AFh to the S10 register. (Master-receiver mode)
(2) Set the ACKBIT bit in the S20 register to 0 (ACK presents) because the data is not the last one.
(3) Write a dummy data to the S00 register
(C) Data reception 2 (data reception)
(In I²C-bus interrupt routine)
(1) Read the received data from the S00 register
(2) Set the ACKBIT bit in the S20 register to 1 (no ACK) because the data is the last one.
(3) Write a dummy data to the S00 register
(D) End of master reception
(In I²C-bus interrupt routine)
(1) Read the received data from the S00 register
(2) Write C0h to the S10 register. (Stop condition standby state)
(3) Write a dummy data to the S00 register (stop condition generated)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 612 of 791