M16C65 Datasheet, PDF (144/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8.2.5 Peripheral Clock Select Register (PCLKR)
8. Clock Generator
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
00 000
Symbol
PCLKR
Address
0012h
After Reset
0000 0011b
Bit Symbol
Bit Name
Function
RW
Timers A and B clock select bit
PCLK0
(clock source for timers A and
B, the dead time timer, and
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
RW
muliti-master I²C-bus interface)
SI/O clock select bit
PCLK1
(clock source for UART0 to
UART2, UART5 to UART7,
0: f2SIO
1: f1SIO
RW
SI/O3, and SI/O4)
—
(b4-b2)
Reserved bits
Set to 0
RW
Clock output function
0: Selected by bits CM01 to CM00
PCLK5 extension bit
in the CM0 register
RW
(valid in single-chip mode) 1: Output f1
—
(b7-b6)
Reserved bits
Set to 0
RW
Write to the PCLKR register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
PCLK5 (Clock Output Function Extension Bit) (b5)
The PCLK5 bit is valid in single-chip mode. Output from the CLKOUT pin is selectable. When the
PCLK5 bit is 1, set bits CM01 to CM00 to 00b. Refer to Table 8.4 “CLKOUT Pin Functions for Single-
Chip Mode”.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 109 of 791