M16C65 Datasheet, PDF (581/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1) Transmit Timing
Transmit/receive clock
TE bit in
1
U2C1 register
0
TI bit in
1
U2C1 register
0
TXD2
Parity error signal
returned from
receiving end
RXD2 pin level ⁽²⁾
TXEPT bit in
1
U2C0 register
0
IR bit in
1
S2TIC register
0
Tc
Data is written to the U2TB register. (Note 1)
Start
bit
Parity
bit
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Data is transferred from the U2TB
register to the UART2 transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
A low-level signal is applied from the
SIM card due to a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
An interrupt
routine
detects the level.
An interrupt routine detects
the level.
The above timing diagram applies when data is
transmitted in the direct format.
• The STPS bit in the U2MR register = 0 (1 stop bit)
• The PRY bit in the U2MR register = 1 (even parity)
• The UFORM bit in the U2C0 register = 0 (LSB first)
• The U2LCH bit in the U2C1 register = 0 (no reverse)
• The U2IRS bit in the U2C1 register = 1 (transmit completed)
(2) Receive Timing
Tc
Transmit/receive clock
Set to 0 by an interrupt request acknowledgement or by a program.
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : Frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : Frequency of U2BRG count source (external clock)
n : Value set to U2BRG
RE bit in
1
U2C1 register
0
Transmit waveform
from
transmitting end
TXD2
RXD2 pin level ⁽³⁾
Start
bit
Parity
bit
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TXD2 provides low-level
output due to a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
RI bit in
U2C1 register
1
0
1
IR bit in
S2RIC register ⁰
Read the U2RB register.
Set to 0 by an interrupt request acknowledgement or by a program.
The above timing diagram applies when data is
received in the direct format.
• The STPS bit in the U2MR register = 0 (1 stop bit)
• The PRY bit in the U2MR register = 1 (even parity)
• The UFORM bit in the U2C0 register = 0 (LSB first)
• The U2LCH bit in the U2C1 register = 0 (no reverse)
• The U2IRS bit in the U2C1 register = 1 (transmit completed)
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : Frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : Frequency of U2BRG count source (external clock)
n : Value set to U2BRG
Notes:
1. Data transmission starts when BRG overflows after a value is set in the U2TB register on the rising edge of the TI bit.
2. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of the transmit waveform from the
TXD2 pin and parity error signal from the receiving end, is generated.
3. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of the transmit waveform from the
transmitting end and parity error signal from the TXD2 pin, is generated.
Figure 23.27 Transmit/Receive Timing in SIM Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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