M16C65 Datasheet, PDF (648/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.10.4 Slave Reception
The slave reception is described in this section. The initial settings described in 225.3.10.1 “Initial
Setting” are assumed to be completed. Figure 25.19 shows the example of slave reception. The
following programs (A) to (C) are executed at the (A) to (C) in Figure 25.19, respectively.
S: Start condition
P: Stop condition
m
S
Slave address
(7 bits)
A: ACK
A: NACK
R: Read
W: Write
s
m
s
WA
Data
(8 bits)
A
m: Master outputs to SDA
s: Slave outputs to SDA
m
sm
Data
(8 bits)
A/A P
SCLMM
SDAMM
IR bit in the IICIC
register
Set to 0 by interrupt request acceptance or by program
(A) Start of slave reception
(B) Data reception 1
(C) Data reception 2
End of slave reception
Figure 25.19 Example of Slave Reception
(A) Slave receive is started.
(In I²C-bus interrupt routine)
(1) Check the content of S10 register. When the TRX bit is 0, the I²C interface is in slave-receiver
mode.
(2) Write a dummy data to the S00 register.
(B) Data reception 1
(In I²C-bus interrupt routine)
(1) Read the received data from the S00 register.
(2) Set the ACKBIT bit in the S20 register to 0 (ACK presents) because the data is not the last one.
(3) Write a dummy data to the S00 register.
(C) Data reception 2
(In I²C-bus interrupt routine)
(1) Read the received data from the S00 register
(2) Set the ACKBIT bit in the S20 register to 1 (no ACK presents) because the data is the last one.
(3) Write a dummy data to the S00 register.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 613 of 791