M16C65 Datasheet, PDF (278/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.7.6 Returning from an Interrupt Routine
The FLG register and PC saved in the stack immediately before entering the interrupt sequence are
restored from the stack by executing the REIT instruction at the end of the interrupt routine. Then, the
CPU returns to the program which was being executed before the interrupt request was accepted.
Restore the other registers saved by a program within the interrupt routine using the POPM or another
instruction before executing the REIT instruction.
The register bank is switched back to the bank used prior to the interrupt sequence by the REIT
instruction.
14.7.7 Interrupt Priority
If two or more interrupt requests occur at the same sampling points (the point in time at which interrupt
requests are detected), the interrupt with the highest priority is acknowledged.
For maskable interrupts (peripheral function interrupts), any priority level can be selected using bits
ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is selected by hardware, with the highest priority interrupt accepted.
The watchdog timer interrupt and other special interrupts have their priority levels set in hardware.
Figure 14.7 shows the Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. When an instruction is executed, control
always branches to the interrupt routine.
Reset
High
NMI
DBC
Watchdog timer,
oscillation stop
and re-oscillation detection,
voltage monitor 1, voltage monitor 2
Peripheral functions
Single-step
Address match
Low
Figure 14.7 Hardware Interrupt Priority
14.7.8 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt among sampled interrupt
requests at the same sampling point.
Figure 14.8 shows the Interrupt Priority Select Circuit 1, and Figure 14.9 shows the Interrupt Priority
Select Circuit 2.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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