M16C65 Datasheet, PDF (620/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
PED (SDAMM Port Function Switch Bit) (b2)
PEC (SCLMM Port Function Switch Bit) (b3)
Bits PEC and PED are enabled when the ES0 bit in the S1D0 register is set to 1 (I²C interface
enabled).
When the PEC bit is set to 1 (output port), the P7_1 bit value is output from the SCLMM pin regardless
of the internal SCL output signal and PD7_1 bit value. When the PED bit is set to 1 (output port), the
P7_0 bit value is output from the SDAMM pin regardless of the internal SDA output signal and PD7_0
bit value.
The signal level on the bus is input to the internal SDA and internal SCL.
When bits P7_1 to P7_0 in the P7 register are read after setting bits PD7_1 and PD7_0 in the PD7
register to 0 (input mode), the level on the bus can be read regardless of the setting values of bits PED
and PEC. Table 25.7 lists SCLMM and SDAMM Pin Functions.
Table 25.7 SCLMM and SDAMM Pin Functions
S1D0 Register
S3D0 Register
Pin
ES0 bit
PED bit PEC bit
P7_1/SCLMM
0
-
-
-
0
1
-
1
P7_0/SDAMM
0
-
-
0
-
1
1
-
–: 0 or 1
Pin Function
I/O port or other peripheral pins
SCLMM (SCL input/output)
Output port (output P7_1 bit value)
I/O port or other peripheral pins
SDAMM (SDA input/output)
Output port (output P7_0 bit value)
SDAM (Internal SDA Output Monitor Bit) (b4)
SCLM (Internal SCL Output Monitor Bit) (b5)
The internal SDA and SCL output signal levels are the same as the output level of the I²C interface
before it has any effect from the external device output. Bits SDAM and SCLM are read only bits.
Should be written with 0.
ICK1-ICK0 (I2C bus System Clock Select Bit) (b7-b6)
Bits ICK1 to ICK0 should be rewritten when the ES0 bit in the S1D0 register is 0 (I²C interface
disabled). The fVIIC is selected by setting all the bits ICK1 to ICK0, bits ICK4 to ICK2 in the S4D0
register, and the PCLK0 bit in the PCLKR register. Refer to 25.3.1.2 “Bit Rate and Duty Cycle”.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 585 of 791