M16C65 Datasheet, PDF (221/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
12. Memory Space Expansion Function
12.3.2 4-Mbyte Mode
In 4-Mbyte mode, the memory space is 4 Mbytes. Set the IRON bit in the PRG2C register to 0 (program
ROM 1 addresses 40000h to 7FFFFh disabled). Bits BSR2 to BSR0 in the DBR register select the bank
number to be accessed to read or write data. Setting the OFS bit to 1 (offset) allows the accessed
address to be offset by 40000h.
In 4-Mbyte mode, the CSi pin function differs depending on the area to be accessed.
12.3.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh
• The CSi signal is output from the CSi pin (same operation as 1-Mbyte mode, except the last
address of the CS1 area is up to 3FFFFh).
12.3.2.2 Addresses 40000h to BFFFFh
• The CS0 pin outputs a low-level signal.
• Pins CS1 to CS3 output the setting values of bits BSR2 to BSR0 (bank number).
Figure 12.3 and Figure 12.4 show the memory mapping and CS areas in 4-Mbyte mode.
Note that banks 0 to 6 are data-only areas. Place programs in bank 7 or the CSi area.
Memory expansion mode
00000h
00400h
XXXXXh
04000h
SFR
Internal RAM ⁽¹⁾
Reserved area
08000h
0D000h
0D800h
0E000h
10000h
14000h
SFR
Data flash ⁽²⁾
Program ROM 2 ⁽³⁾
Microprocessor mode
SFR
Internal RAM ⁽¹⁾
Reserved area
CS3 (16 Kbytes)
SFR
Reserved, external area ⁽⁴⁾
Reserved, external area ⁽⁵⁾
CS2
27000h
28000h
40000h
Reserved area
External area
Reserved area
External area
CS1 (96 Kbytes)
Other than the CS area (512 Kbytes x 8 banks)
C0000h
D0000h
YYYYYh
FFFFFh
Reserved area
Program ROM 1 ⁽¹⁾
CS0 (memory expansion mode : 64 Kbytes)
CS0
Notes :
1. When the PM13 bit in the PM1 register is 0, 15 Kbytes of the internal RAM and 192 Kbytes of
the internal ROM can be used. See the table below for addresses XXXXXh and YYYYYh.
Internal RAM
Program ROM 1
Capacity Address XXXXXh Capacity Address YYYYYh
12 Kbytes
20 Kbytes
31 Kbytes
033FFh
03FFFh
03FFFh
128 Kbytes
256 Kbytes
384 Kbytes
E0000h
D0000h
D0000h
47 Kbytes 03FFFh 512 Kbytes D0000h
640 Kbytes D0000h
768 Kbytes D0000h
2. When the PM10 bit is 0, this area is used as an external area; when 1, used as internal ROM
(data flash).
3. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area;
when 0, used as internal ROM (program ROM 2).
4. When the PM10 bit is 0, this area is used as an external area; when 1, used as a reserved area.
5. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area;
when 0, used as a reserved area.
6. The CS0 pin outputs a low signal, and pins CS1 to CS3 output a bank number.
Figure 12.3 Memory Mapping and CS Areas in 4-Mbyte Mode (PM13 = 0)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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