M16C65 Datasheet, PDF (585/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Some interrupts of UART0 to UART2 and UART5 to UART7 share interrupt vectors and interrupt
control registers with other peripheral functions. When using these interrupts, select them by interrupt
source select registers. Table 23.27 lists Interrupt Select in UART0 to UART2 and UART5 to UART7.
Table 23.27 Interrupt Select in UART0 to UART2 and UART5 to UART7
Interrupt Source
UART0 start/stop condition detection, bus collision detection
UART1 start/stop condition detection, bus collision detection
UART5 start/stop condition detection, bus collision detection
UART5 transmission, NACK
UART6 start/stop condition detection, bus collision detection
UART6 transmission, NACK
UART7 start/stop condition detection, bus collision detection
UART7 transmission, NACK
Interrupt Source Select Register Settings
Register
Bit
Setting Value
IFSR2A
IFSR26
1
IFSR2A
IFSR27
1
IFSR3A
IFSR33
0
IFSR3A
IFSR34
0
IFSR3A
IFSR35
0
IFSR3A
IFSR36
0
IFSR2A
IFSR24
0
IFSR2A
IFSR25
0
An interrupt request may be generated by bit contents change in the following modes.
• Special mode 1 (I²C mode)
Set the IR bit in the interrupt control register of UARTi to 0 (interrupt not requested), when the
following bits are changed:
Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register,
the IICM2 bit in the UiSMR2 register, the CKPH bit in the UiSMR3 register
• Special mode 4 (SIM mode)
After reset, when bits U2IRS and U2ERE in the U2C1 register are set to 1 (transmission
completed) and 1 (interrupt not requested) respectively, a transmission interrupt request is
generated. In SIM mode, set these bits first, and then set the IR bit in the S2TIC register to 0
(interrupt not requested).
23.4.2 Reception Interrupt
• The case that bits SMD2 to SMD0 in the UiMR register are not set to 010b (I²C mode)
When the RI bit in the UiC1 register is changed from 0 (no data in the UiRB register) to 1 (data
present in the UiRB register), the IR bit in the SiRIC register is automatically set to 1 (interrupt
requested).
If an overrun error occurs (when the RI bit is 1, the next data is received), the RI bit remains 1,
and therefore, the IR bit in the SiRIC register remains unchanged.
• The case that bits SMD2 to SMD0 in the UiMR register are set to 010b (I²C mode)
When the RI bit in the UiC1 register is changed from 0 (no data in the UiRB register) to 1 (data
present in the UiRB register), the IR bit in the SiRIC register is automatically set to 1 (interrupt
requested).
When an overrun error occurs, the IR bit in the SiRIC register also becomes 1.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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