M16C65 Datasheet, PDF (539/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.10 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7)
UARTi Special Mode Register (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0SMR, U1SMR, U2SMR
U5SMR, U6SMR, U7SMR
Address
0247h, 0257h, 0267h
0287h, 0297h, 02A7h
Bit Symbol
Bit Name
Function
After Reset
X000 0000b
X000 0000b
RW
IICM I²C mode select bit
0 : Other than I²C mode
1 : I²C mode
RW
ABC
Arbitration lost detect flag
control bit
0 : Update per bit
1 : Update per byte
RW
BBS Bus busy flag
0 : Stop-condition detected
1 : Start-condition detected (busy)
RW
—
(b3)
Reserved bit
Set to 0
RW
ABSCS
Bus collision detect sampling 0 : Rising edge of transmit/receive clock
clock select bit
1 : Underflow signal of timer Aj
RW
ACSE
Auto clear function select bit 0 : No auto clear function
of transmit enable bit
1 : Auto clear at occurrence of bus collision
RW
SSS
Transmit start condition
select bit
0 : Not synchronized to RXDi
1 : Synchronized to RXDi
RW
—
(b7)
No register bit. If necessary, set to 0. Read as undefined value
—
BBS (Bus Busy Flag) (b2)
The BBS bit is set to 0 by a program. (It remains unchanged even if 1 is written.)
ABSCS (Bus Collision Detect Sampling Clock Select Bit) (b4)
When the ABSCS bit is 1, the combinations of UARTi and timer Aj are as follows:
UART0, UART6: Underflow signal of timer A3
UART1, UART7: Underflow signal of timer A4
UART2, UART5: Underflow signal of timer A0
SSS (Transmit Start Condition Select Bit) (b6)
When a transmit starts, the SSS bit is set to 0 (not synchronized to RXDi).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 504 of 791