M16C65 Datasheet, PDF (577/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.5 Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated by one byte of UART mode waveform.
Table 23.23 lists the Registers Used and Settings in IE Mode. Figure 23.26 shows the Bus Collision
Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2, 5 to 7) output level and RXDi pin input level do not match, a UARTi bus
collision detect interrupt request is generated.
Use bits IFSR26 and IFSR27 in the IFSR2A register to enable the UART0/UART1 bus collision detect
function.
Table 23.23 Registers Used and Settings in IE Mode
Register
Bits
Function
UiTB
0 to 8
Set transmission data.
UiRB ⁽³⁾
0 to 8
Reception data can be read.
OER, FER, PER, SUM
Error flag
UiBRG
0 to 7
Set bit rate.
UiMR
SMD2 to SMD0
Set to 110b.
CKDIR
Select internal clock or external clock.
STPS
Set to 0.
PRY
Invalid because PRYE is 0
PRYE
Set to 0.
IOPOL
Select the TXD and RXD input/output polarity.
UiC0
CLK1, CLK0
Select the count source for the UiBRG register.
CRS
Invalid because CRD is 1
TXEPT
Transmit register empty flag
CRD
Set to 1.
NCH
Select TXDi pin output format. ⁽²⁾
CKPOL
Set to 0.
UFORM
Set to 0.
UiC1
TE
Set to 1 to enable transmission.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
UjIRS ⁽¹⁾
Select the source of UARTj transmit interrupt.
UjRRM ⁽¹⁾, UiLCH, UiERE
Set to 0.
UiSMR
0 to 3, 7
Set to 0.
ABSCS
Select the sampling timing to detect a bus collision.
ACSE
Set to 1 to use the auto clear function of transmit enable bit.
SSS
Select the transmit start condition.
UiSMR2
0 to 7
Set to 0.
UiSMR3
0 to 7
Set to 0.
UiSMR4
0 to 7
Set to 0.
IFSR2A
IFSR26, IFSR27
Set to 1.
UCON
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt.
U0RRM, U1RRM
Set to 0.
CLKMD0
Invalid because CLKMD1 is 0
CLKMD1, RCSP, 7
Set to 0.
i = 0 to 2, 5 to 7
Notes:
1. Set bits 4 and 5 in registers U0C0 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the UCON register.
2. The TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0 register. If necessary, set to
0.
3. Set the bits not listed above to 0 when writing to the registers in IE mode.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 542 of 791