M16C65 Datasheet, PDF (578/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1) ABSCS bit in UiSMR register (bus collision detect sampling clock select)
(i = 0 to 2, 5 to 7)
When ABSCS is 0, bus collision is determined at the rising edge of the transmit/receive clock.
Transmit/receive clock
TXDi
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
Trigger signal is applied to the TAjIN pin
Timer Aj
When ABSCS is 1, bus collision is determined when timer Aj (one-shot timer mode) underflows.
Timer Aj: Timer A3 in UART0; timer A4 in UART1; timer A0 in UART2
timer A0 in UART5; timer A3 in UART6; timer A4 in UART7
(2) ACSE bit in UiSMR register (auto clear of transmit enable bit)
Transmit/receive clock
TXDi
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
IR bit in UiBCNIC and
BCNIC register
TE bit in UiC1 register
When ACSE bit is 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to 0
(transmission disabled) when the
IR bit in the UiBCNIC register is 1
(unmatching detected).
(3) SSS bit in the UiSMR register (transmit start condition select)
When SSS bit is 0, the serial interface starts sending data one transmit/receive
clock cycle after the transmission enable condition is met.
Transmit/receive clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TXDi
CLKi
TXDi
Transmit enable conditions are met.
When SSS bit is 1, the serial interface starts sending data at the rising edge of RXDi. ⁽¹⁾
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
(2)
RXDi
Notes :
1. The falling edge of RXDi when IOPOL is 0; the rising edge of RXDi when IOPOL is 1.
2. The transmit conditions must be met before the falling edge of RXD.
The above diagram applies when IOPOL is 1 (reversed).
i = 0 to 2, 5 to 7
Figure 23.26 Bus Collision Detect Function-Related Bits
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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