M16C65 Datasheet, PDF (744/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
30. Flash Memory
30.8 CPU Rewrite Mode
In CPU rewrite mode, the flash memory can be rewritten when the CPU executes software commands.
Program ROM 1, program ROM 2, and data flash can be rewritten with the MCU mounted on a board and
without using a ROM programmer.
The program and block erase commands are executed only in individual block areas of program ROM 1,
program ROM 2, and data flash.
Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite
mode. Table 30.10 lists the differences between EW0 mode and EW1 mode.
Table 30.10 EW0 Mode and EW1 Mode
Item
EW0 Mode
EW1 Mode
Operating mode
• Single-chip mode
Single-chip mode
• Memory expansion mode
Rewrite control
Program allocatable
area
• Program ROM 1
• Program ROM 2
• External area
• Program ROM 1
• Program ROM 2
Rewrite Control
The rewrite control program must be The rewrite control program can be
Program Executable transferred to an area other than the executed in program ROM 1 and
Area
flash memory (e.g., RAM) before being program ROM 2.
executed.
Rewritable area
• Program ROM 1
• Program ROM 1
• Program ROM 2
• Program ROM 2
• Data flash
• Data flash
Excluding blocks with the rewrite control
program
Software command None
restriction
• Program and block erase commands
Do not execute in a block with the
rewrite control program.
• Read status register command
Do not execute.
Mode after program Read status register mode
Read array mode
or erase
State during auto Hold state is not maintained.
Hold state is maintained. (I/O ports
write and auto erase
maintains the state before the command
execution) ⁽¹⁾
Flash memory
status detection
• Read bits FMR00, FMR06, and
FMR07 in the FMR0 register by a
Read bits FMR00, FMR06, and FMR07
in the FMR0 register by a program.
program.
• Execute the read status register
command, and then read bits SR7,
SR5 and SR4 in the status register.
Note:
1. Do not generate an interrupt (except NMI interrupt) or start a DMA transfer.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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