M16C65 Datasheet, PDF (662/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
26. Consumer Electronics Control (CEC) Function
26.2.4 CEC Function Control Register 4 (CECC4)
CEC Function Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CECC4
Address
0353h
After Reset
00h
Bit Symbol
CRISE0
Bit Name
CRISE1 Rising timing select bit
CCTRXISDE2N
CABTEN
Error low pulse output
enabled bit
Function
RW
b2 b1 b0
0 0 0: Standard value
RW
0 0 1: Standard value - 30 μs
0 1 0: Standard value - 60 μs
0 1 1: Standard value - 90 μs
RW
1 0 0: Standard value - 120 μs
1 0 1: Standard value - 150 μs
1 1 0: Standard value - 180 μs RW
1 1 1: Standard value + 30 μs
0: Disabled
1: Enabled
RW
CFALL0
RW
Falling timing select bit
Refer to the following.
CFALL1
RW
CREGFLG Receive edge detect flag
0: Not detected
1: Detected
RO
CABTWEN
Error low pulse output wait
control bit
0: Low pulse output regardless of
CEC signal state
1: Low pulse output at the rising edge
RW
of the CEC signal
CRISE2-CRISE0 (Rising Timing Select Bit) (b2-b0)
The rising timing of the signal in transmission is selected. The rising timing is common to the start bit
and data bit.
CABTEN (Error Low Pulse Output Enable Bit) (b3)
When the CABTEN bit is set to 1 (low pulse output enabled in receive error), 3.6 ms of low pulse is
output if the data bit in reception is out of the acceptable range.
Output timing is selected by the CABTWEN bit.
CFALL1-CFALL0 (Falling Timing Select Bit) (b5-b4)
The falling timing of the signal in transmission is specified.
Table 26.7 Falling Timing of Signal in Transmission
Bits CFALL1 to CFALL0
00b
01b
10b
11b
Start Bit
Standard value
Standard value - 40 μs
Standard value - 100 μs
Standard value - 160 μs
Falling Timing
Data Bit
Standard value
Standard value - 190 μs
Standard value - 250 μs
Standard value - 310 μs
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 627 of 791