M16C65 Datasheet, PDF (517/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
Table 22.20 Registers and Setting Values in Input Capture Mode (Simultaneous Count Operation)
(2/2)
Register
PMCiINT
Bit
CPINT
REINT
DRINT
BFULINT
PTHDINT
PTDINT
TIMINT
PMCiCPC
PMCiCPD
PMCiHDPMIN
PMCiHDPMAX
PMCiD0PMIN
PMCiD0PMAX
PMCiD1PMIN
PMCiD1PMAX
PMCiTIM
SDINT
CPN0
CPN1
CPN2
CPEN
0 to 7
0 to 10
0 to 10
0 to 7
0 to 7
0 to 7
0 to 7
0 to 15
PMCiBC
0 to 15
PMCiDAT0 to
0 to 7
PMCiDAT5
PMC0RBIT
0 to 5
i = 0, 1
-: No register bit in PMC1
Function
PMC0
PMC1
0
-
0
0
0
0
0
-
0
0
0
0
Set to 1 when using timer
Set to 1 when using timer
measure interrupt
measure interrupt
0
-
000b
-
0
00h
0000h
0000h
00h
00h
00h
00h
Measured value of pulse
period or width can be read
Counter value can be read
Not used
Not used
-
-
0000h
0000h
00h
00h
00h
00h
Measured value of pulse
period or width can be read
Counter value can be read
Not used
Not used
22.3.5.1 Setting Procedure
To start or stop counting, follow procedures below:
(1) Set the EN bit in the PMC0CON0 register to 1 (0 to stop).
(2) Set the EN bit in the PMC1CON0 register to 1 (1 to stop).
(3) Wait for two cycles of count source.
(4) Confirm that the ENFLG bit in the PMC0CON2 register is 1 (0 to stop). (The ENFLG bit in the
PMC1CON2 register is disabled)
22.3.5.2 Count Operation
In input capture mode, the counter counts from 0000h to FFFFh, and then return to 0000h to continue
counting.
When the counter becomes 0000h after FFFFh, the CEFLG bit in the PMCiCON2 register becomes 1
(counter overflow) and holds 1.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 482 of 791