M16C65 Datasheet, PDF (646/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.10.2 Master Transmission
The master transmission is described in this section. The initial settings described in 25.3.10.1 “Initial
Setting” are assumed to be completed. Figure 21.17 shows the operation of master transmission.
The following programs (A) to (C) are executed at the (A) to (C) in Figure 25.17, respectively.
S: Start condition
P: Stop condition
m
S
Slave address
(7 bits)
A: ACK
A: NACK
R: Read
W: Write
s
m
s
WA
Data
(8 bits)
A
m: Master outputs to SDA
s: Slave outputs to SDA
m
sm
Data
(8 bits)
A/A P
SCLMM
SDAMM
IR bit in the IICIC
register
Set to 0 by interrupt request acceptance or by program
(A) Slave address transmission
(B) Data transmission
(C) End of master transmission
Stop condition
Figure 25.17 Example of Master Transmission
(A) Slave address transmission
(1) The BB bit in the S10 register must be 0 (bus free).
(2) Write E0h to the S10 register. (Start condition standby)
(3) Write a slave address to the seven most significant bits (MSB) and a 0 to the least significant bit
(LSB). (Start condition generated, then slave address transmitted)
(B) Data transmission
(in I²C-bus interrupt routine)
(1) Write transmit data to the S00 register. (data transmission)
(C) Completion of Master transmission
(in I²C-bus interrupt routine)
(1) Write C0h to the S10 register. (Stop condition standby state)
(2) Write a dummy data to the S00 register. (stop condition generated)
When the transmission is completed or ACK is not returned from slave device (NACK returned), master
transmission should be completed as above.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 611 of 791