M16C65 Datasheet, PDF (660/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
26. Consumer Electronics Control (CEC) Function
26.2.3 CEC Function Control Register 3 (CECC3)
CEC Function Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CECC3
Address
0352h
After Reset
XXXX 0000b
Bit Symbol
Bit Name
Function
RW
CTXDEN Transmit enable bit
0: Disabled
1: Enabled
RW
CRXDEN Receive enable bit
0: Disabled
1: Enabled
RW
CREGCLR
Receive edge detect flag
clear bit
The CREGFLG bit in the CECC4
register becomes 0 by setting 1 to
this bit
RW
CEOMI EOM disable bit
0: EOM enabled
1: EOM disabled (EOM ignored)
RW
—
(b7-b4)
No register bits. If necessary, set to 0. Read as undefined value
—
CTXDEN (Transmit Enable Bit) (b0)
CRXDEN (Receive Enable Bit) (b1)
When changing the value of these bits, transmission/reception is enabled or disabled after one or more
cycles of the clock source elapses.
CREGCLR (Receive Edge Detect Flag Clear Bit) (b2)
The CREGFLG bit in the CECC4 register is set to 0 by setting the CREGCLR bit to 1 when the CEC
input is Hi-Z. When the CEC input is low, the CREGFLG bit remain unchanged even if the CREGCLR
bit is set to 1.
The CREGCLR bit holds the written value.
To set the CREGCLR bit to 1 in order to set the CREGFLG bit to 0 again, write 0 and then 1.
Figure 26.2 shows Operation of Bits CREGFLG and CREGCLR.
CEC
CREGFLG bit
Become 1 when
CEC is low.
CREGCLR bit
The CREGFLG bit
becomes 0 by setting
the CREGCLR bit to 0
when CEC is high.
Become 1 when CEC
is low.
(The CREGFLG bit
remain unchanged even
if the CREGCLR bit is set
to 1)
CREGCLR: Bit in the CECC3 register
CREGFLG: Bit in the CECC4 register
Figure 26.2 Operation of Bits CREGFLG and CREGCLR
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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