M16C65 Datasheet, PDF (139/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8. Clock Generator
CM02 (Wait Mode Peripheral Function Clock Stop Bit) (b2)
The CM02 bit is used to stop the peripheral function clock f1 in wait mode. The peripheral functions fC,
fC32, fOCO-S, fOCO-F, and fOCO40M are not affected by the CM02 bit.
When the PM21 bit in the PM2 register is set to 1 (clock change disabled), the CM02 bit remains
unchanged even when written to.
CM03 (XCIN-XCOUT Drive Capacity Select Bit) (b3)
Setting the driving capacity to low while sub-clock oscillation is stable reduces power consumption.
The CM03 bit is set to 1 (high) while the CM04 bit is 0 (P8_6 and P8_7 are I/O ports), or when entering
stop mode.
CM04 (Port XC Select Bit) (b4)
The CM03 bit is set to 1 (high) while the CM04 bit is 0 (P8_6 and P8_7 are I/O ports).
CM05 (Main Clock Stop Bit) (b5)
The CM05 bit is provided to stop the main clock when selecting the low power mode or 125 kHz on-chip
oscillator low power mode, or when stopping the main clock at 40 MHz on-chip oscillator mode. The
CM05 bit cannot be used to detect whether the main clock is stopped or not. Refer to 8.7 “Oscillation
Stop/Re-Oscillation Detect Function” for the main clock stop detection.
When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM05 bit remains unchanged
even when written to.
CM06 (Main Clock Division Select Bit) (b6)
The CM06 bit becomes 1 (divide-by-8 mode) under the following conditions:
• When entering stop mode
• When the CM07 bit is 1 (sub clock used as CPU clock) and the CM05 bit is 1 (main clock off)
CM07 (System Clock Select Bit) (b7)
The CPU clock source and the peripheral function clock f1 depend on combinations of the bit status of
the CM07 bit, the CM11 bit in the CM1 register, and the CM21 bit in the CM2 register. When the CM07
bit is 0 (main clock, PLL clock or on-chip oscillator clock used as CPU clock), the CPU clock source and
the peripheral function clock f1 can be selected by combinations of the bit status of the CM11 bit and
the CM21 bit. When the CM07 bit is 1 (sub clock used as CPU clock), the CPU clock source is fC, and
the peripheral function clock f1 can be selected by combinations of the bit status of bits CM11 and
CM21.
When setting the PM21 bit in the PM2 register to 1 (clock change disabled), set the CM07 bit to 0 (main
clock) before setting the PM21 bit to 1. When the PM21 bit is set to 1, this bit remains unchanged even
when written to.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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