M16C65 Datasheet, PDF (635/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.3 Generation of Stop Condition
Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I²C interface enabled).
(1) Write C0h to the S10 register.
The I²C interface enters the stop condition standby state and the SDAMM pin is driven low.
(2) Write a dummy data to the S00 register.
A stop condition is generated.
The stop condition generation timing depends on the modes (standard clock mode or high-speed clock
mode). Figure 25.8 shows Sop Condition Generation Timing. Refer to Table 25.13 “Setup/Hold Time for
Start/Stop Condition Generation” for setup/hold time.
Write signal to the S00 register
SCLMM
SDAMM
BB bit in the S10 register
Setup
Hold
Setup
BB bit
Figure 25.8 Sop Condition Generation Timing
The S10 register or S00 register should not be written until the BB bit in the S10 register becomes 0
(bus free) after the instructions to generate a stop condition (refer to above (2)) are executed.
If the SCLMM pin input signal becomes low until the BB bit in the S10 register becomes 0 (bus free)
from the instruction to generate a stop condition is executed and the SCLMM pin becomes high-level,
the internal SCL output becomes low. In this case, perform one of the procedures below to stop the low
signal output from the SCLMM pin (leave the SCLMM pin open).
• Generate a stop condition (perform the procedures (1) and (2) described previously).
• Set the ES0 bit in the S1D0 register to 0 (I²C interface disabled).
• Write a 1 to the IHR bit (I²C interface reset).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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