M16C65 Datasheet, PDF (119/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
7. Voltage Detector
VW1C2 (Voltage Change Detection Flag) (b2)
The VW1C2 bit is enabled when the VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit
enabled). The VW1C2 remains unchanged even if 1 is written by a program.
Condition to become 0:
• Writing 0 by a program
Condition to become 1:
Table 7.4 Conditions Under which the VW1C2 Bit Becomes 1
Bit Setting
WV1C1 VW1C6 VW1C7
Conditions under Which the VW1C2 Bit Becomes 1
0
0
0 or 1 The VW1C3 bit changes (from 0 to 1 and from 1 to 0).
1
1
The VW1C3 bit changes from 1 to 0.
1
0
0
The VW1C3 bit changes from 0 to 1.
1
The VW1C3 bit changes from 1 to 0.
1
1
The VW1C3 bit changes from 1 to 0.
Note:
1. Do not set values not listed above.
VW1C3 (Voltage Detection 1 Signal Monitor Flag) (b3)
The VW1C3 bit is enabled when the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2
circuits enabled) and the VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit enabled).
Condition to become 0:
• VCC1 < Vdet1 (when the VW12E bit is 1 and the VC26 bit is 1)
Condition to become 1:
• VCC1 ≥ Vdet1 (when the VW12E bit is 1 and the VC26 bit is 1)
• The VC26 bit in the VCR2 register is 0 (voltage detection 1 circuit disabled).
VW1C6 (Voltage Monitor 1 Circuit Mode Select Bit) (b6)
The VW1C6 bit is enabled when the VW1C0 bit is 1 (voltage monitor 1 interrupt/reset enabled).
VW1C7 (Voltage Monitor 1 Interrupt/Reset Generation Condition Select Bit) (b7)
The voltage monitor 1 interrupt/reset generation condition can be selected by the VW1C7 bit when the
VW1C6 bit is 0 (voltage monitor 1 interrupt at Vdet1 passage) and the VW1C1 bit is 1 (digital filter
disabled).
When the VW1C6 bit is 1 (voltage monitor 1 reset at Vdet1 passage), set the VW1C7 bit to 1 (when
VCC1 reaches Vdet1 or below). (Do not set the VW1C7 bit to 0.)
When the VW1C1 bit is 0 (digital filter enabled), regardless of the VW1C7 bit setting, the voltage
monitor 1 interrupt is generated when VCC1 reaches Vdet1 or above and also when VCC1 reaches
Vdet1 or below.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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