M16C65 Datasheet, PDF (560/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.2.5 TXD and RXD I/O Polarity Reverse Function
This function reverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all
input/output data (including bits for start, stop, and parity) are reversed. Figure 23.16 shows TXD and
RXD I/O Polarity Reversal.
(1) IOPOL bit in the UiMR register = 0 (no reverse)
Transmit/receive ^High
clock
Low
TXDi
High
(no reverse)
Low
RXDi
High
(no reverse)
Low
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) IOPOL bit in the UiMR register = 1 (reverse)
Transmit/receive ^High
clock
Low
TXDi
High
(reverse)
Low
RXDi
High
(reverse)
Low
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST: Start bit
P : Parity bit
SP: Stop bit
i = 0 to 2, 5 to 7
The above applies under the following conditions.
- The UFORM bit in the UiC0 register is 0 (LSB first).
- The STPS bit in the UiMR register is 0 (1 stop bit).
- The PRYE bit in the UiMR register is 1 (parity enabled).
- The UiLCH bit in the UiC1 register is 0 (serial data logic not reversed).
Figure 23.16 TXD and RXD I/O Polarity Reversal
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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