M16C65 Datasheet, PDF (502/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
PMCi internal input signal
EN bit
Bits TYP1 to TYP0 are 00b (period measurement)
Counter operation
a
b
Count starts
PMCiTIM register
a
Overflow at the
setting value
Count stops Count starts
b
IR bit
The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0.
Bits TYP1 to TYP0 are 01b (high level width measurement)
Counter
operation
a
b
c
Overflow at the
setting value
Count stops Count starts
PMCiTIM register
a
b
c
IR bit
The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0.
Bits TYP1 to TYP0 are 10b (pulse width measurement)
Counter
operation
a
b
c
d
e
Overflow at the
setting value
Count stops Count starts
PMCiTIM register
IR bit
DRFLG
a
b
c
d
e
The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0.
i = 0, 1
EN: Bit in the PMCiCON0 register
Frame ends
Next frame stars
DRFLG: Bit in the PMCiSTS register
IR: Bit in the PMCiIC register
Overflow at the setting value: Counter value is larger than values of registers PMCiHDPMAX, PMCiD0PMAX, and
PMCiD1MAX.
The above diagram shows an instance in which the following conditions are met:
y The TIMINT bit in the PMCiINT register is 1(timer measure interrupt enabled)
y Bits other than the TIMINT bit in the PMCiINT register are 0 (interrupt disabled)
y The COINT bit in the PMCiCON2 register is 0 (interrupt disabled)
Figure 22.6 Difference of Operations in Receive Modes (Pattern Match Mode)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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