M16C65 Datasheet, PDF (606/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.2 Registers Descriptions
Table 25.4 lists registers associated with multi-master I²C-bus interface. When the CM07 bit in the CM0
register is set to 1 (sub clock is CPU clock), registers listed in Table 25.4 should not be accessed. Set
them after the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock).
Table 25.4 Register Configuration
Address Register Name
0012h Peripheral Clock Select Register
02B0h I2C0 Data Shift Register
02B2h I2C0 Address Register 0
02B3h I2C0 Control Register
02B4h I2C0 Clock Control Register
02B5h I2C0 Start/Stop Condition Control Register
02B6h I2C0 Control Register 1
02B7h I2C0 Control Register 2
02B8h I2C0 Status Register 0
02B9h I2C0 Status Register 1
02BAh I2C0 Address Register 1
02BBh I2C0 Address Register 2
Symbol
PCLKR
S00
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
S11
S0D1
S0D2
After Reset
0000 0011b
XXh
0000 000Xb
00h
00h
0001 1010b
0011 0000b
00h
0001 000Xb
00h
0000 000Xb
0000 000Xb
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 571 of 791