M16C65 Datasheet, PDF (313/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
16. DMAC
16.3.5 Single Transfer Mode
In single transfer mode, the transfer stops when the DMAi transfer counter underflows. Figure 16.3
shows Operation Example in Single Transfer Mode.
Single Transfer Mode
Bus
CPU
DMA
CPU
DMA
CPU
DMA
CPU
DMAS bit
When a transfer begins, the DMAS bit is set to 0.
Underflow
TCRi bit Undefined 02h
01h
Reload
IR bit
00h
FFh
Set to 0 by an interrupt request acknowledgement
or by a program.
DMAE bit
Set to 1 by a program.
i = 0 to 3
DMAS, DMAE : Bits in the DMiCON register
IR : Bit in the DMiIC register
The above diagram applies when the register bit is set as follows:
Value in the TCRi register = 02h (there are three transfers).
Figure 16.3 Operation Example in Single Transfer Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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