M16C65 Datasheet, PDF (567/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi
Initial value and
end value are high.
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1, DMA3 request),
NACK interrupt
Transfer to UiRB register
b15 b9 b8 b7
b0
...
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(2) IICM2 = 0, CKPH = 1 (clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi
Initial value and
end value are low.
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1, DMA3 request),
NACK interrupt
Transfer to UiRB register
b15 b9 b8 b7
b0
...
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
SCLi
SDAi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
Initial value and
end value are high.
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt Transmit
(DMA1, DMA3 interrupt
request)
Transfer to UiRB register
b15 b9 b8 b7
b0
...
D0
D7 D6 D5 D4 D3 D2 D1
UiRB register
(4) IICM2 = 1, CKPH = 1
1st bit 2nd bit 3rd bit 4th bit
SCLi
5th bit
6th bit
7th bit
8th bit
9th bit
Initial value and
end value are low.
SDAi
D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Receive interrupt
(DMA1, DMA3
request)
Transmit interrupt
i = 0 to 2, 5 to 7
Transfer to UiRB register
b15 b9 b8 b7
b0
...
D0
D7 D6 D5 D4 D3 D2 D1
UiRB register
(read by reception interrupt)
Transfer to UiRB register
b15 b9 b8 b7
b0
...
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(read by transmission interrupt)
This diagram applies when the following condition is met.
· The CKDIR bit in the UiMR register = 1 (slave selected)
Figure 23.19 Transfer to UiRB Register and Interrupt Timing
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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