M16C65 Datasheet, PDF (582/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Figure 23.28 shows an Example of SIM Interface Connection. Connect TXD2 and RXD2, and then
connect a pull-up resistor.
MCU
TXD2
RXD2
SIM card
Figure 23.28 Example of SIM Interface Connection
23.3.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (error signal
output).
The parity error signal is output when a parity error is detected while receiving data. A low-level signal
is output from the TXD2 pin in the timing shown in Figure 23.29. If the U2RB register is read while
outputting a parity error signal, the PER bit is cleared to 0 (no parity error) and at the same time the
TXD2 output again goes high.
When transmitting, a transmission complete interrupt request is generated at the falling edge of the
transmit/receive pulse that immediately follows the stop bit. Therefore, whether or not a parity error
signal has been returned can be determined by reading the port that shares the RXD2 pin in a
transmission complete interrupt routine.
Transmit/receive clock ^High
Low
RXD2 ^High
Low
TXD2 ^High
Low
RI bit in ¹
U2C1 register 0
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(NOTE 1)
This timing diagram applies to the case where the direct format is implemented.
Note:
1. The output of the MCU is in the high-impedance state (pulled up externally).
ST : Start bit
P : Even parity
SP : Stop bit
Figure 23.29 Parity Error Signal Output Timing
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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