M16C65 Datasheet, PDF (634/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
The start condition generation timing depends on the modes (standard clock mode or high-speed clock
mode). Figure 25.7 shows Start Condition Generation Timing.
Table 25.13 lists Setup/Hold Time for Start/Stop Condition Generation.
Write signal to the S00 register
SCLMM
SDAMM
BB bit in the S10 register
Setup
Hold
Setup
BB bit
Figure 25.7 Start Condition Generation Timing
Table 25.13 Setup/Hold Time for Start/Stop Condition Generation
Item
STSPSEL Bit Standard Clock Mode
High-speed Clock Mode
fVIIC cycles
fVIIC = 4 MHz fVIIC cycles fVIIC = 4MHz
Setup time 0 (short mode) 20
5.0 μs
10
2.5 μs
1 (long mode) 52
13.0 μs
26
6.5 μs
Hold time 0 (short mode) 20
5.0 μs
10
2.5 μs
1 (long mode) 52
13.0 μs
26
6.5 μs
BB bit set/ -
reset time
3.375 μs ⁽¹⁾
3.5
-S----S----C------v---a---l-u----e----^–-----1-- + 2
2
0.875 μs
-: 0 or 1
STSPSEL: Bit in the S2D0 register
SSC value: Value of bits SSC4 to SSC0 in the S2D0 register
Note:
1. Example value when bits SSC4 to SSC0 are 11000b.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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