M16C65 Datasheet, PDF (533/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.5 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7)
UARTi Bit Rate Register (i = 0 to 2, 5 to 7)
b7
b0
Symbol
U0BRG, U1BRG, U2BRG
U5BRG, U6BRG, U7BRG
Address
0249h, 0259h, 0269h
0289h, 0299h, 02A9h
Function
If set value is n, UiBRG divides the count source by n + 1
After Reset
Undefined
Undefined
Setting Range
RW
00h to FFh
WO
Write to the UiBRG register while serial interface is neither transmitting nor receiving.
Use MOV instruction to write to the UiBRG register.
Write to the UiBRG register after setting bits CLK1 to CLK0 in the UiC0 register.
23.2.6 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7)
UARTi Transmit/Receive Mode Register (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR, U1MR, U2MR
U5MR, U6MR, U7MR
Address
0248h, 0258h, 0268h
0288h, 0298h, 02A8h
After Reset
00h
00h
Bit Symbol
Bit Name
Function
RW
SMD0
b2 b1 b0
0 0 0 : Serial interface disabled
RW
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I²C mode
SMD1 Serial I/O mode select bit _{1 0 0 : UART mode character bit length is 7 bits} RW
1 0 1 : UART mode character bit length is 8 bits
SMD2
1 1 0 : UART mode character bit length is 9 bits
Do not set values other than the above
RW
CKDIR
Internal/external clock
select bit
0 : Internal clock
1 : External clock
RW
STPS
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
RW
Valid when PRYE is 1
PRY Odd/even parity select bit 0 : Odd parity
RW
1 : Even parity
PRYE Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
IOPOL
TXD, RXD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
RW
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 498 of 791