M16C65 Datasheet, PDF (651/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
Table 25.16 I²C-bus Interrupts
Interrupt Interrupt Source
Associated Bits (Register)
Interrupt
enabled
Interrupt
request
Interrupt
Control
Register
I²C-bus ^{Completion of data transmit/receive}
—
Interrupt ^{When the ACKCKL = 0,}
Detection of the falling edge of the last clock of
transmit/receive data through SCLMM pin
When the ACKCKL = 1,
Detection of the falling edge of ACK clock
through SCLMM pin
PIN (S10)
IICIC
Data reception (before ACK clock)
WIT (S3D0)
Detection of the falling edge of the last clock of
transmit/receive data through SCLMM pin
Detection of slave address match
—
Received slave address matches bits SAD6 to
SAD0 in slave-receiver mode with addressing
format
(AAS bit in the S10 register = 1)
Detection of general call
General call in slave-receiver mode with
addressing format
(ADR0 bit in the S10 register = 1)
Completion of receiving slave address in
slave-receiver mode with free format
Stop condition detected
SIM (S3D0) SCPIN (S4D0)
Timeout detected
TOE (S4D0) TOF (S4D0)
SCL/ Detection of the falling edge or rising edge of —
—
SCLDAIC
SDA
input/output signal for the SCLMM or SDAMM
interrupt pin
Refer to 14.7 “Interrupt Control”. Table 25.17 lists Registers Associated with I²C Interface Interrupts.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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