M16C65 Datasheet, PDF (547/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.1.1 Transmit/Receive Register Initialization
When the transmit/receive register needs to be initialized due to an interrupted transmission/
reception, follow the procedures below.
• Initializing the UiRB register (i = 0 to 2, 5 to 7)
(1) Set the RE bit in the UiC1 register to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode).
(4) Set the RE bit in the UiC1 register to 1 (reception enabled).
• Initializing the UiTB register (i = 0 to 2, 5 to 7)
(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(2) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode).
(3) Write a 1 to the RE bit in the UiC1 register (transmission enabled), regardless of the value of the
TE bit in the UiCi register.
23.3.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the transmit/receive clock polarity.
Figure 23.6 shows the Transmit/Receive Clock Polarity.
(1) CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the
receive data taken in at the rising edge of the transmit/receive clock)
CLKi
TXDi
A high-level signal is output from the CLKi
pin during no transmission/reception.
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0 D1 D2 D3 D4 D5 D6 D7
(2) CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at
the falling edge of the transmit/receive clock)
A low-level signal is output from the CLKi
pin during no transmission/reception.
CLKi
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0 D1 D2 D3 D4 D5 D6 D7
The above applies under the following conditions.
The CKDIR bit in the UiMR register is 0 (internal clock),
the UFORM bit in the UiC0 register is 0 (LSB first), and
the UiLCH bit in the UiC1 register is 0 (no reverse).
i = 0 to 2, 5 to 7
Figure 23.6 Transmit/Receive Clock Polarity
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 512 of 791