M16C65 Datasheet, PDF (254/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
Note
Do not use INT3 to INT5 for the 80-pin package.
14. Interrupts
14.1 Introduction
Table 14.1 lists Types of Interrupt, and Table 14.2 lists I/O Pins. The pins shown in Table 14.2 are external
interrupt input pins. Refer to the peripheral functions for the pins related to the peripheral functions.
Table 14.1 Types of Interrupt
Type
Interrupt
Function
Software
Undefined instruction (UND
instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
An interrupt is generated by executing an instruction.
Non-maskable interrupt ⁽²⁾
Hardware Specific
NMI
Interrupt by the MCU hardware
Watchdog timer
Non-maskable interrupt ⁽²⁾
Oscillation stop and re-oscillation
detection
Voltage monitor 1
Voltage monitor 2
Address match
Single step ⁽¹⁾
DBC ⁽¹⁾
Peripheral INT, timers, etc.
Interrupt by the peripheral functions in the MCU
function (See 14.6.2 “Relocatable Vector Maskable interrupt
Tables”.)
(interrupt priority level: 7 levels) ⁽²⁾
Notes:
1.
2.
This interrupt is provided exclusively for developers and should not be used.
Maskable interrupt: Interrupt status (enabled or disabled) can be selected by the interrupt
enable flag (I flag).
Interrupt priority can be changed by the interrupt priority level.
Non-maskable interrupt: Interrupt status (enabled or disabled) cannot be selected by the interrupt
enable flag (I flag).
Interrupt priority cannot be changed by the interrupt priority level.
Table 14.2 I/O Pins
Pin Name
I/O Type
Function
NMI
I
NMI interrupt input
INTi
I ⁽¹⁾
INTi interrupt input
KI0 to KI3
I ⁽¹⁾
Key input
i = 0 to 7
Note:
1. Set the port direction bits which share pins to 0 (input mode).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 219 of 791