M16C65 Datasheet, PDF (248/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
13.3.8 NMI/SD Digital Filter Register (NMIDF)
13. Programmable I/O Ports
NMI/SD Digital Filter Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
NMIDF
Address
0369h
After Reset
XXXX X000b
Bit Symbol
Bit Name
Function
RW
NMIDF0
NMI/SD filter
NMIDF1 sampling clock
select bit
NMIDF2
b2 b1 b0
0 0 0 : No filter
RW
0 0 1 : CPU clock divided by 2
0 1 0 : CPU clock divided by 4
0 1 1 : CPU clock divided by 8
RW
1 0 0 : CPU clock divided by 16
1 0 1 : CPU clock divided by 32
1 1 0 : CPU clock divided by 64
RW
1 1 1 : CPU clock divided by 128
—
(b7-b3)
No register bits. If necessary, set to 0. Read as undefined value
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REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 213 of 791