M16C65 Datasheet, PDF (150/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8. Clock Generator
8.3.2 PLL Clock
The PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for
the CPU and peripheral function clocks.
After reset, the PLL frequency synthesizer is stopped.
The PLL clock is the main clock divided by the selected values of bits PLC05 to PLC04 in the PLC0
register, and then multiplied by the selected values of bits PLC02 to PLC00. Set bits PLC05 to PLC04
to fit divided frequency between 2 MHz and 5 MHz. Figure 8.3 shows Relation between Main Clock and
PLL Clock.
Main clock
Divided by n
Multiplied by m
PLL clock
(1)
(2)
n : 1, 2, 4 (selected by bits PLC05 to PLC04 in the PLC0 register)
m : 2, 4, 6, 8 (selected by bits PLC02 to PLC00 in the PLC0 register)
Notes :
1. Set the frequency divided by n to between 2 MHz and 5 MHz.
2. Set 10 MHz ≤ PLL clock frequency ≤ 32 MHz
Figure 8.3 Relation between Main Clock and PLL Clock
Bits PLC05 to PLC04 and bits PLC02 to PLC00 can be set only once after reset. Table 8.5 lists Example
Settings for PLL Clock Frequencies.
Table 8.5 Example Settings for PLL Clock Frequencies
Main Clock
Setting Value
Bits PLC05 to PLC04
Bits PLC02 to PLC00
10 MHz
01b (divide-by-2)
010b (multiply-by-4)
5 MHz
00b (not divided)
010b (multiply-by-4)
12 MHz
10b (divide-by-4)
100b (multiply-by-8)
6 MHz
01b (divide-by-2)
100b (multiply-by-8)
16 MHz
10b (divide-by-4)
100b (multiply-by-8)
8 MHz
01b (divide-by-2)
100b (multiply-by-8)
PLL Clock
20 MHz
24 MHz
32 MHz
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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