M16C65 Datasheet, PDF (579/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.6 Special Mode 4 (SIM Mode) (UART2)
SIM interface devices can communicate in UART mode. Both direct and inverse formats are
available. The TXD2 pin outputs a low-level signal when a parity error is detected.
Table 23.24 lists the SIM Mode Specifications. Table 23.25 lists the Registers Used and Settings in
SIM Mode.
Table 23.24 SIM Mode Specifications
Item
Specification
Data formats
• Direct format
• Inverse format
Transmit/receive clock • The CKDIR bit in the U2MR register = 0 (internal clock): fi/(16(n + 1))
fi = f1SIO, f2SIO, f8SIO, f32SIO
n = Setting value of the U2BRG register 00h to FFh
• The CKDIR bit = 1 (external clock): fEXT/(16(n + 1))
fEXT = input from the CLK2 pin
n = Setting value of the U2BRG register 00h to FFh
Transmission start
To start transmission, satisfy the following requirements.
conditions
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register
= 0 (data present in the U2TB register)
Reception start
To start reception, satisfy the following requirements.
conditions
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
Interrupt request
generation timing ⁽²⁾
• Transmission
When the serial interface completed sending data from the UART2 transmit
register (the U2IRS bit =1)
• Reception
When transferring data from the UART2 receive register to the U2RB register
(at completion of reception)
Error detection
• Overrun error ⁽¹⁾
This error occurs if the serial interface starts receiving the next unit of data
before reading the U2RB register and receives the bit one before the last stop
bit of the next unit of data.
• Framing error ⁽³⁾
This error occurs when the number of stop bits set is not detected.
• Parity error ⁽³⁾
During reception, if a parity error is detected, parity error signal is output from
the TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2
pin when a transmission interrupt occurs.
• Error sum flag
This flag is set to 1 when an overrun, framing, or parity error occurs.
Notes:
1. If an overrun error occurs, the received data of the U2RB register will be undefined. The IR bit in
the S2RIC register remains unchanged.
2. After reset, a transmit interrupt request is generated by setting the U2IRS bit to 1 (transmission
completed) and the U2ERE bit to 1 (error signal output) in the U2C1 register. Therefore, when
using SIM mode, set the IR bit to 0 (interrupt not requested) after setting the bits.
3. The timing that the framing error flag and the parity error flag are set is detected when data is
transferred from the UART2 receive register to the U2RB register.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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