M16C65 Datasheet, PDF (545/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Table 23.8 lists Registers Used and Settings in Clock Synchronous Serial I/O Mode.
Table 23.8 Registers Used and Settings in Clock Synchronous Serial I/O Mode
Register
Bits
Function
UiTB ^{(2) 0 to 7}
Set transmission data
UiRB ^{(2) 0 to 7}
Reception data can be read.
OER
Overrun error flag
UiBRG 0 to 7
Set bit rate.
UiMR ^{(2) SMD2 to SMD0 Set to 001b.}
CKDIR
Select the internal clock or external clock.
IOPOL
Set to 0.
UiC0
CLK1 to CLK0 Select the count source for the UiBRG register.
CRS
If CTS or RTS is used, select which function to use.
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function.
NCH
Select TXDi pin output mode. ⁽¹⁾
CKPOL
Select the transmit/receive clock polarity.
UFORM
Select LSB first or MSB first.
UiC1
TE
Set to 1 to enable transmission/reception.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
UjIRS
Select source of UARTj transmit interrupt.
UjRRM
Set to 1 to use continuous receive mode.
UiLCH
Set to 1 to use inverted data logic.
UiERE
Set to 0.
UiSMR 0 to 7
Set to 0.
UiSMR2 0 to 7
Set to 0.
UiSMR3 0 to 2
Set to 0.
NODC
Select clock output mode.
4 to 7
Set to 0.
UiSMR4 0 to 7
Set to 0.
UCON U0IRS
Select source of UART0 transmit interrupt.
U1IRS
Select source of UART1 transmit interrupt.
U0RRM
Set to 1 to use continuous receive mode.
U1RRM
Set to 1 to use continuous receive mode.
CLKMD0
Select the transmit/receive clock output pin when CLKMD1 is 1.
CLKMD1
Set to 1 to output UART1 transmit/receive clock from two pins.
RCSP
Set to 1 to separate the CTS0/RTS signal of UART0.
7
Set to 0.
IFSR3A IFSR34
Set to 0 to use UART5 transmit interrupt.
IFSR36
Set to 0 to use UART6 transmit interrupt.
IFSR2A ^IFSR25
Set to 0 to use UART7 transmit interrupt.
i = 0 to 2, 5 to 7 j = 2, 5 to 7
Notes:
1. The TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0
register. If necessary, set to 0.
2. Set bits not listed above to 0 when writing to the registers in clock synchronous serial I/O mode.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 510 of 791