M16C65 Datasheet, PDF (564/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Table 23.16 Registers Used and Settings in I²C Mode (1/2)
Register
Bits
Master
Function
Slave
UiTB
0 to 7
Set transmission data.
Set transmission data.
UiRB ^{(2) 0 to 7}
8
Reception data can be read.
ACK or NACK is set in this bit.
Reception data can be read.
ACK or NACK is set in this bit.
ABT
Arbitration lost detection flag
Invalid
OER
Overrun error flag
Overrun error flag
UiBRG 0 to 7
Set a bit rate.
Invalid
UiMR ^{(2) SMD2 to}
SMD0
Set to 010b.
Set to 010b.
CKDIR
Set to 0.
Set to 1.
IOPOL
Set to 0.
Set to 0.
UiC0
CLK1, CLK0 Select the count source for the UiBRG
register.
Invalid
CRS
Invalid because CRD is 1
Invalid because CRD is 1
TXEPT
Transmit register empty flag
Transmit register empty flag
CRD ⁽³⁾
Set to 1.
Set to 1.
NCH
Set to 1. ⁽¹⁾
Set to 1. ⁽¹⁾
CKPOL
Set to 0.
Set to 0.
UFORM
Set to 1.
Set to 1.
UiC1
TE
Set to 1 to enable transmission.
Set to 1 to enable transmission.
TI
Transmit buffer empty flag
Transmit buffer empty flag
RE
Set to 1 to enable reception.
Set to 1 to enable reception.
RI
Reception complete flag
Reception complete flag
UjIRS
Set to 1.
Set to 1.
UjRRM,
UiLCH,
UiERE
Set to 0.
Set to 0.
UiSMR IICM
Set to 1.
Set to 1.
ABC
Select the timing that arbitration lost is
detected.
Invalid
BBS
Bus busy flag
Bus busy flag
3 to 7
Set to 0.
Set to 0.
UiSMR2 IICM2
See Table 23.18 “I²C Mode Functions”.
See Table 23.18 “I²C Mode Functions”.
CSC
Set to 1 to enable clock synchronization. Set to 0.
SWC
Set to 1 to fix SCLi output to low at the
falling edge of the 9th bit of clock.
Set to 1 to fix SCLi output to low at the falling
edge of the 9th bit of clock.
ALS
Set to 1 to stop SDAi output when
Set to 0.
arbitration lost is detected.
STAC
Set to 0.
Set to 1 to initialize UARTi at start condition
detection.
SWC2
Set to 1 to forcibly pull SCLi output low.
Set to 1 to forcibly pull SCLi output low.
SDHI
Set to 1 to disable SDAi output.
Set to 1 to disable SDAi output.
7
Set to 0.
Set to 0.
i = 0 to 2, 5 to 7
j = 2, 5 to 7
Notes:
1. The TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0 register. If
necessary, set to 0.
2. Set the bits not listed above to 0 when writing in I²C mode.
3. when using UART1 in I²C mode, to enable the CTS/RTS separate function of UART0, set the CRD bit in the
U1C0 register to 0 (CTS/RTS enabled) and the CRS bit to 0 (CTS input).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 529 of 791