M16C65 Datasheet, PDF (615/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
ACKBIT (ACK bit) (b6)
The ACK bit is enabled when the I²C interface is a master-receiver or slave-receiver. It is also enabled
when receiving a slave address. When receiving a slave address, the SDAMM pin level during the ACK
clock pulse is determined by the combination of bits ALS and ACKBIT in the S1D0 register and the
received slave address.
When receiving data, the SDAMM pin level during the ACK clock pulse is determined by the ACKBIT
bit. Table 25.5 lists the SDAMM Pin Level during the ACK Clock Pulse.
Table 25.5 SDAMM Pin Level during the ACK Clock Pulse
Received
Content
ALS Bit in the
S1D0 Register
ACKBIT Bit in the
S20 Register
Slave Address Content
SDAMM Pin Level at
ACK Clock
Slave
0
0
Matched with bits SAD6 L (ACK)
Address
to SAD0 in any of
registers S0D0 to S0D2
0000000b
L (ACK)
Others
H (NACK)
1
—
H (NACK)
1
0
—
L (ACK)
1
—
H (NACK)
Data
—
0
—
L (ACK)
1
—
H (NACK)
ACKCLK (ACK Clock Bit) (b7)
When the ACKCLK bit is 1 (ACK clock presents), an ACK clock is generated immediately after one-byte
data is transmitted or received (8 clocks).
When the ACKCLK bit is 0 (no ACK clock), no ACK clock is generated after one-byte data is
transmitted or received (8 clocks). At the falling edge of the data transmission/reception (the falling
edge of the 8th clock), the IR bit in the IICIC register becomes 1 (interrupt requested).
The ACKCLK bit should not be rewritten during transmission/reception.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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