M16C65 Datasheet, PDF (140/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8.2.3 System Clock Control Register 1 (CM1)
8. Clock Generator
System Clock Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
CM1
Address
0007h
After Reset
0010 0000b
Bit Symbol
Bit Name
Function
RW
CM10 All clock stop control bit
0 : Clock on
1 : All clocks off (stop mode)
RW
CM11 System clock select bit 1
0 : Main clock
1 : PLL clock
RW
—
(b2)
Reserved bit
Set to 0
RW
CM13
XIN-XOUT feedback resistor
select bit
0 : Internal feedback resistor connected
1 : Internal feedback resistor not connected
RW
CM14
125 kHz on-chip oscillator stop 0 : 125 kHz on-chip oscillator on
bit
1 : 125 kHz on-chip oscillator off
RW
CM15
XIN-XOUT drive capacity
select bit
0 : Low
1 : High
RW
CM16
b7 b6
0 0 : No division mode
Main clock division select bit 1 0 1 : Divide-by-2 mode
RW
CM17
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
Rewrite the CM1 register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
Refer to Table 9.3 “Clock Related Bit Setting and Modes” to select a clock and a mode.
CM10 (All Clock Stop Control Bit) (b0)
When the CM11 bit is 1 (PLL clock), or the CM20 bit in the CM2 register is 1 (oscillation stop detection
function enabled), do not set the CM10 bit to 1.
When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM10 bit remains unchanged
even when written to (stop mode is not entered). When the CSPRO bit in the CSPR register is 1
(watchdog timer count source protection mode), the CM10 bit remains unchanged even when written to
(stop mode is not entered).
CM11 (System Clock Select Bit) (b1)
The CM11 bit is valid when the CM21 bit in the CM2 register is set to 0 (main clock or PLL clock).
The CPU clock source and the peripheral function clock f1 can be selected by the CM11 bit when the
CM07 bit is 0 (main clock, PLL clock, or on-chip oscillator clock used as CPU clock). The peripheral
function clock f1 can be selected by the CM11 bit when the CM07 bit is 1 (sub clock used as CPU
clock).
When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM11 bit remains unchanged
even when written to.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 105 of 791