M16C65 Datasheet, PDF (309/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
16. DMAC
16.3 Operations
16.3.1 DMA Enabled
When data transfer starts after setting the DMAE bit in the DMiCON register (i = 0 to 3) to 1 (enabled),
the DMAC operates as listed below. If 1 is written to the DMAE bit when it is already set to 1, the DMAC
also performs the following operation.
• The forward address pointer is reloaded with the SARi register value when the DSD bit in the
DMiCON register is 1 (forward), or the DARi register value when the DAD bit in the DMiCON
register is 1 (forward).
• The DMAi transfer counter is reloaded with the DMAi transfer counter reload register value.
16.3.2 DMA Request
The DMAC can generate a DMA request as triggered by the request source that is selected with the
DMS bit and bits DSEL4 to DSEL0 in the DMiSL register (i = 0 to 3) on either channel. Table 16.7 lists
the Timing at Which the DMAS Bit Changes State.
Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of
whether or not the DMAE bit is set. If the DMAE bit is set to 1 (enabled) when this occurs, the DMAS bit
is set to 0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 by
a program (writing a 1 has no effect).
If the DMAE bit is 1, the DMAS bit in almost all cases is 0 when read in a program, because a data
transfer starts immediately after a DMA request is generated. Read the DMAE bit to determine whether
the DMAC is enabled. When a DMA request transfer cycle is shorter than a DMA transfer cycle, the
number of transfer requests and the number of transfers do not agree.
When the peripheral function is selected as a DMA source, relations with interrupts are as follows:
• DMA transfers are not affected by the I flag or interrupt control registers. DMA requests are always
accepted even when interrupt requests are not accepted.
• The IR bit in the interrupt control register retains its value when a DMA transfer is accepted.
Table 16.7 Timing at Which the DMAS Bit Changes State
DMA Source
Software trigger
External factor
Peripheral function
i = 0 to 3
DMAS Bit in the DMiCON Register
Timing at Which the Bit is Set to 1
Timing at Which the Bit is Set to 0
When the DSR bit in the DMiSL register • Immediately before a data transfer
is set to 1
When an input edge of pins INT0 to
INT7 agrees with what is selected by
starts
• When set by writing a 0 by a program
bits DSEL4 to DSEL0 in the DMiSL
register.
When an interrupt request of the
peripheral function selected by bits
DSEL4 to DSEL0 and DMS in the
DMiSL register is generated. (If the IR
bit in an interrupt control register is 0,
the timing is when 0 is changed to 1.)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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