M16C65 Datasheet, PDF (297/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
15. Watchdog Timer
15.4.2 Count Source Protection Mode Enabled
The fOCO-S is used as the watchdog timer count source when the count source protection mode is
enabled.
Table 15.4 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled).
Table 15.4 Watchdog Timer Specifications (Count Source Protection Mode Enabled)
Item
Count source
Count operation
Cycle
Specification
fOCO-S
(The 125 kHz on-chip oscillator clock automatically starts oscillating.)
Decrement
W------a---t--c---h----d---o---g-----t--i-m-----e----r---c---o----u---n---t----v---a---l-u----e-----(--4---0---9----6---)
fOCO-S
(The watchdog timer cycle is approximately 32.8 ms.)
Watchdog timer
• Reset (Refer to 6. “Resets”.)
counter initial value _{• Write 00h, and then FFh to the WDTR register.}
setting
• Underflow
Count start
Set the WDTON bit in the OFS1 address to select the watchdog timer operation
conditions
after reset.
• WDTON bit is 1 (watchdog timer is stopped after reset)
The watchdog timer and prescaler stop after reset and count starts by writing to
the WDTS register.
• WDTON bit is 0 (watchdog timer starts automatically after reset)
The watchdog timer and prescaler start counting automatically after reset.
Count stop
None (Count does not stop in wait mode or by bus hold once count starts. The MCU
condition
does not enter stop mode.)
Operation when Watchdog timer reset (See 6.4.8 “Watchdog Timer Reset”).
timer underflows
When the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), the watchdog
timer counter underflows every 4096 cycles because three low-order bits are not used.
Also when the CSPRO bit is set to 1 (count source protection mode enabled), the following bits change:
• The CM14 bit in the CM1 register becomes 0 (125 kHz on-chip oscillator on). It remains
unchanged even if 1 is written, and the 125 kHz on-chip oscillator does not stop.
• The PM12 bit in the PM1 register becomes 1 (watchdog timer reset when watchdog timer counter
underflows).
• The CM10 bit in the CM1 register remains unchanged even if 1 is written, and the MCU does not
enter stop mode.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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